1) Field of the Invention
This invention relates generally to fabrication of non-volatile memory devices and to improved methods of fabricating SONOS type non-volatile memory devices.
2) Description of the Prior Art
Electrically erasable programmable non-volatile memory comes in different types, for example, EEPROM of a floating gate type, a metal-nitride-oxide-silicon (MNOS) type, a metal-oxide-nitride-oxide-silicon (MONOS) type, and a silicon-oxide-nitride-oxide-silicon (SONOS) type.
The SONOS-type EEPROM has a stacked structure typically comprising a lower oxide layer, a nitride layer, an upper oxide layer, and a polysilicon layer. The lower oxide layer is a tunnel oxide layer, the nitride layer 30 is a memory (storage) layer, and the upper oxide layer 40 is a blocking layer for preventing the loss of a stored charge. The polysilicon layer is a gate. The lower oxide layer, the nitride layer, the upper oxide layer, and the polysilicon layer are sequentially formed on a substrate in which isolation regions are formed. Source/drain regions are formed at both sides of the stacked structure in the substrate.
The SONOS-type EEPROM can be used in a compact semiconductor memory cell because it needs less voltage to program and erase than an EEPROM of the floating gate type. To achieve a more highly integrated SONOS-type EEPROM, the size of a memory cell needs to be reduced.
There is a challenge to produce SONOS devices with increase reliability.
Relevant technical developments in the patent literature can be gleaned by considering the following.
U.S. Patent Application 2002 0192910—A1—Ramsbey, Mark T.; et al. Dec. 19, 2002—Simultaneous formation of charge storage and bitline to wordline isolation—the patent forms a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a gate dielectric in the periphery region; forming buried bitlines in the core region; and forming gates in the core region and the periphery region.
U.S. Pat. No. 6,730,564 Ramsbey, et al.—Salicided gate for virtual ground arrays—shows a process for a SONOS. The patent appears to pattern the ONO layer before depositing the poly.
U.S. 20040014289 A1 Woo, Won Sic—Method for manufacturing semiconductor device and the device thereof—shows a process for MONOS/SONOS device.
U.S. Patent Application 20040009645 A1—Yoo, Tae-kwang—shows a EEPROM and method of fabricating the same a method of fabricating a SONOS-type EEPROM increases memory cell performance and reduces memory cell size.